URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] [dbg_cpu_defines.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5614d 10h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
153	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7411d 16h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
147	CPU_WR_CTRL and CPU_RD_CTRL defines changed.	igorm	7414d 16h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
141	data_cnt_lim length changed to reduce number of warnings.	igorm	7419d 15h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
139	New release of the debug interface (3rd. release).	igorm	7422d 09h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
138	Temp version before changing dbg interface.	igorm	7428d 13h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
101	Almost finished.	mohor	7493d 13h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
100	* empty log message *	mohor	7494d 15h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v