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[/] [dbg_interface/] [tags/] [asyst_3/] [rtl/] [verilog/] [dbg_defines.v] - Rev 158

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158 root 5602d 03h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
154 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7399d 08h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
144 Port names and defines for the supported CPUs changed. igorm 7406d 11h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
139 New release of the debug interface (3rd. release). igorm 7410d 02h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
138 Temp version before changing dbg interface. igorm 7416d 06h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7468d 12h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
117 Define name changed. mohor 7478d 08h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7506d 07h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
73 CRC logic changed. mohor 7567d 06h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
71 Mbist support added. simons 7569d 13h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
65 WB_CNTL register added, some syncronization fixes. simons 7603d 08h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
63 Three more chains added for cpu debug access. simons 7623d 09h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
57 Multiple cpu support added. simons 7651d 10h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8101d 08h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8203d 14h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
27 Warnings from synthesys tools fixed. mohor 8253d 12h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
23 Trace disabled by default. mohor 8261d 13h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8305d 13h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8326d 08h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v
9 Working version. Few bugs fixed, comments added. mohor 8330d 12h /dbg_interface/tags/asyst_3/rtl/verilog/dbg_defines.v

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