URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_cpu.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5590d 01h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_cpu.v
133	This commit was manufactured by cvs2svn to create tag 'highland_ver1'.		7412d 04h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_cpu.v
123	All flipflops are reset.	mohor	7461d 07h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_cpu.v
121	Port signals are all set to zero after reset.	mohor	7464d 07h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_cpu.v
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7467d 14h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_cpu.v
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7469d 03h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_cpu.v
102	New version.	mohor	7469d 03h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_cpu.v
101	Almost finished.	mohor	7469d 04h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_cpu.v
100	* empty log message *	mohor	7470d 06h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_cpu.v