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[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5590d 01h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
133	This commit was manufactured by cvs2svn to create tag 'highland_ver1'.		7412d 04h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7456d 11h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
123	All flipflops are reset.	mohor	7461d 07h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
117	Define name changed.	mohor	7466d 07h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7467d 14h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
106	Sensitivity list updated.	simons	7468d 12h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
101	Almost finished.	mohor	7469d 04h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
99	cpu registers added.	mohor	7470d 06h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
95	Temp version.	mohor	7471d 22h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7494d 06h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
73	CRC logic changed.	mohor	7555d 05h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
67	Lower two address lines must be always zero.	simons	7590d 07h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
65	WB_CNTL register added, some syncronization fixes.	simons	7591d 06h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
63	Three more chains added for cpu debug access.	simons	7611d 07h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
57	Multiple cpu support added.	simons	7639d 09h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7906d 07h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7933d 18h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8089d 06h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
44	Signal names changed to lower case.	mohor	8104d 08h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v

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[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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