OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [new_debug/] [bench/] [verilog/] [dbg_tb.v] - Rev 158

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 root 5590d 01h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
98 This commit was manufactured by cvs2svn to create tag 'new_debug'. 7471d 09h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
96 Working. mohor 7471d 10h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
95 Temp version. mohor 7471d 22h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
93 tmp version. mohor 7473d 09h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
92 temp version. mohor 7476d 13h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
91 tmp version. mohor 7477d 08h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
90 tmp version. mohor 7478d 03h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
89 temp4 version. mohor 7479d 09h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
88 temp3 version. mohor 7480d 04h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
87 tmp2 version. mohor 7481d 09h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
80 New version of the debug interface. Not finished, yet. mohor 7494d 06h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
73 CRC logic changed. mohor 7555d 05h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
63 Three more chains added for cpu debug access. simons 7611d 07h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8089d 06h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
38 Few outputs for boundary scan chain added. mohor 8145d 06h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
36 Structure changed. Hooks for jtag chain added. mohor 8149d 05h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8289d 09h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
15 bs_chain_o added. mohor 8291d 10h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v
13 Signal names changed to lowercase. mohor 8292d 11h /dbg_interface/tags/new_debug/bench/verilog/dbg_tb.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.