URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] [dbg_register.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5637d 14h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_register.v
78	This commit was manufactured by cvs2svn to create tag 'old_debug'.		7602d 16h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_register.v
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7981d 07h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_register.v
46	Asynchronous reset used instead of synchronous.	mohor	8145d 01h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_register.v
44	Signal names changed to lower case.	mohor	8151d 21h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_register.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8298d 23h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_register.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8336d 22h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_register.v
2	Initial official release.	mohor	8372d 20h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_register.v