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[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5602d 03h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
78	This commit was manufactured by cvs2svn to create tag 'old_debug'.		7567d 05h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
73	CRC logic changed.	mohor	7567d 07h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
67	Lower two address lines must be always zero.	simons	7602d 09h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
65	WB_CNTL register added, some syncronization fixes.	simons	7603d 08h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
63	Three more chains added for cpu debug access.	simons	7623d 09h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
57	Multiple cpu support added.	simons	7651d 11h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7918d 09h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7945d 20h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8101d 08h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
44	Signal names changed to lower case.	mohor	8116d 10h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
43	Intentional error removed.	mohor	8121d 10h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8121d 12h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8157d 13h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
36	Structure changed. Hooks for jtag chain added.	mohor	8161d 08h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8191d 11h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
32	Stupid bug that was entered by previous update fixed.	mohor	8192d 10h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
31	trst synchronization is not needed and was removed.	mohor	8192d 10h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8203d 15h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v
28	TDO and TDO Enable signal are separated into two signals.	mohor	8239d 12h	/dbg_interface/tags/old_debug/rtl/verilog/dbg_top.v

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[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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