URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] [dbg_registers.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5592d 02h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_registers.v
48	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8091d 07h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_registers.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8091d 07h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_registers.v
44	Signal names changed to lower case.	mohor	8106d 09h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_registers.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8253d 11h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_registers.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8291d 10h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_registers.v
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8295d 12h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_registers.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8322d 07h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_registers.v
2	Initial official release.	mohor	8327d 08h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_registers.v