URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] [dbg_sync_clk1_clk2.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5581d 16h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_sync_clk1_clk2.v
48	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8080d 21h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_sync_clk1_clk2.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8243d 01h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_sync_clk1_clk2.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8281d 00h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_sync_clk1_clk2.v
2	Initial official release.	mohor	8316d 22h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_sync_clk1_clk2.v