URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_10/] [rtl/] [verilog/] [dbg_trace.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5701d 17h	/dbg_interface/tags/rel_10/rtl/verilog/dbg_trace.v
76	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7666d 20h	/dbg_interface/tags/rel_10/rtl/verilog/dbg_trace.v
73	CRC logic changed.	mohor	7666d 21h	/dbg_interface/tags/rel_10/rtl/verilog/dbg_trace.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8363d 02h	/dbg_interface/tags/rel_10/rtl/verilog/dbg_trace.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8401d 01h	/dbg_interface/tags/rel_10/rtl/verilog/dbg_trace.v
9	Working version. Few bugs fixed, comments added.	mohor	8430d 03h	/dbg_interface/tags/rel_10/rtl/verilog/dbg_trace.v
8	Asynchronous set/reset not used in trace any more.	mohor	8431d 01h	/dbg_interface/tags/rel_10/rtl/verilog/dbg_trace.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8431d 23h	/dbg_interface/tags/rel_10/rtl/verilog/dbg_trace.v
2	Initial official release.	mohor	8436d 23h	/dbg_interface/tags/rel_10/rtl/verilog/dbg_trace.v