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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5585d 11h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
109	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7463d 00h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7463d 00h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
106	Sensitivity list updated.	simons	7463d 22h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
101	Almost finished.	mohor	7464d 14h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
99	cpu registers added.	mohor	7465d 17h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
95	Temp version.	mohor	7467d 08h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7489d 16h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
73	CRC logic changed.	mohor	7550d 15h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
67	Lower two address lines must be always zero.	simons	7585d 17h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
65	WB_CNTL register added, some syncronization fixes.	simons	7586d 17h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
63	Three more chains added for cpu debug access.	simons	7606d 17h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
57	Multiple cpu support added.	simons	7634d 19h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7901d 17h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7929d 05h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8084d 17h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
44	Signal names changed to lower case.	mohor	8099d 18h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
43	Intentional error removed.	mohor	8104d 18h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8104d 20h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8140d 21h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v

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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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