URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_5/] [sim/] [rtl_sim/] [run/] [do.do] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5648d 04h	/dbg_interface/tags/rel_5/sim/rtl_sim/run/do.do
62	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7697d 10h	/dbg_interface/tags/rel_5/sim/rtl_sim/run/do.do
36	Structure changed. Hooks for jtag chain added.	mohor	8207d 08h	/dbg_interface/tags/rel_5/sim/rtl_sim/run/do.do
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8347d 12h	/dbg_interface/tags/rel_5/sim/rtl_sim/run/do.do
5	Trace fixed. Some registers changed, trace simplified.	mohor	8378d 10h	/dbg_interface/tags/rel_5/sim/rtl_sim/run/do.do
2	Initial official release.	mohor	8383d 10h	/dbg_interface/tags/rel_5/sim/rtl_sim/run/do.do