URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] [verilog/] [dbg_register.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5586d 13h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
64	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7607d 19h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7930d 06h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
46	Asynchronous reset used instead of synchronous.	mohor	8094d 00h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
44	Signal names changed to lower case.	mohor	8100d 20h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8247d 22h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8285d 21h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
2	Initial official release.	mohor	8321d 19h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v