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[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] [verilog/] [dbg_registers.v] - Rev 158

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158 root 5615d 00h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7636d 06h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
61 Lapsus fixed. simons 7664d 06h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
59 Reset value for riscsel register set to 1. simons 7664d 07h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
57 Multiple cpu support added. simons 7664d 08h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7958d 18h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8114d 06h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
44 Signal names changed to lower case. mohor 8129d 07h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8276d 10h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8314d 09h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8318d 10h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
5 Trace fixed. Some registers changed, trace simplified. mohor 8345d 06h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v
2 Initial official release. mohor 8350d 07h /dbg_interface/tags/rel_6/rtl/verilog/dbg_registers.v

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