URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] [verilog/] [dbg_trace.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5648d 08h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_trace.v
64	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7669d 14h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_trace.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8309d 17h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_trace.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8347d 17h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_trace.v
9	Working version. Few bugs fixed, comments added.	mohor	8376d 18h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_trace.v
8	Asynchronous set/reset not used in trace any more.	mohor	8377d 16h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_trace.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8378d 14h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_trace.v
2	Initial official release.	mohor	8383d 14h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_trace.v