URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_crc8_d1.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5581d 00h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
49	This commit was manufactured by cvs2svn to create tag 'sdram_test_working'.		8080d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
44	Signal names changed to lower case.	mohor	8095d 07h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
41	Function changed to logic because of some synthesis warnings.	mohor	8108d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
26	Warnings from synthesys tools fixed.	mohor	8232d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8242d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8280d 08h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
9	Working version. Few bugs fixed, comments added.	mohor	8309d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
2	Initial official release.	mohor	8316d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v