URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_defines.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5580d 23h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
49	This commit was manufactured by cvs2svn to create tag 'sdram_test_working'.		8080d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8080d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8182d 11h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
27	Warnings from synthesys tools fixed.	mohor	8232d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
23	Trace disabled by default.	mohor	8240d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8284d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8305d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
9	Working version. Few bugs fixed, comments added.	mohor	8309d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8311d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
2	Initial official release.	mohor	8316d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v