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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5580d 23h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
49	This commit was manufactured by cvs2svn to create tag 'sdram_test_working'.		8080d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8080d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
44	Signal names changed to lower case.	mohor	8095d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
43	Intentional error removed.	mohor	8100d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8100d 08h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8136d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
36	Structure changed. Hooks for jtag chain added.	mohor	8140d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8170d 07h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
32	Stupid bug that was entered by previous update fixed.	mohor	8171d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
31	trst synchronization is not needed and was removed.	mohor	8171d 07h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8182d 11h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
28	TDO and TDO Enable signal are separated into two signals.	mohor	8218d 08h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
25	trst signal is synchronized to wb_clk_i.	mohor	8233d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
22	Register length fixed.	mohor	8240d 10h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
21	CRC is returned when chain selection data is transmitted.	mohor	8241d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8242d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8254d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
18	Reset signals are not combined any more.	mohor	8256d 18h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8280d 08h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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