URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_trace.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5580d 23h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_trace.v
49	This commit was manufactured by cvs2svn to create tag 'sdram_test_working'.		8080d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_trace.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8242d 08h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_trace.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8280d 07h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_trace.v
9	Working version. Few bugs fixed, comments added.	mohor	8309d 08h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_trace.v
8	Asynchronous set/reset not used in trace any more.	mohor	8310d 07h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_trace.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8311d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_trace.v
2	Initial official release.	mohor	8316d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_trace.v