URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [tap_top.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5580d 23h	/dbg_interface/tags/sdram_test_working/rtl/verilog/tap_top.v
49	This commit was manufactured by cvs2svn to create tag 'sdram_test_working'.		8080d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/tap_top.v
45	tdo_padoen_o changed to tdo_padoe_o. Signal is active high.	mohor	8095d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/tap_top.v
40	Signal tdo_padoe_o changed back to tdo_padoen_o.	mohor	8122d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/tap_top.v
39	tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just not named correctly.	mohor	8123d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/tap_top.v
38	Few outputs for boundary scan chain added.	mohor	8136d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/tap_top.v
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8136d 08h	/dbg_interface/tags/sdram_test_working/rtl/verilog/tap_top.v
36	Structure changed. Hooks for jtag chain added.	mohor	8140d 03h	/dbg_interface/tags/sdram_test_working/rtl/verilog/tap_top.v