URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [timescale.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5580d 22h	/dbg_interface/tags/sdram_test_working/rtl/verilog/timescale.v
49	This commit was manufactured by cvs2svn to create tag 'sdram_test_working'.		8080d 03h	/dbg_interface/tags/sdram_test_working/rtl/verilog/timescale.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8280d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/timescale.v