OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] [verilog/] [dbg_tb.v] - Rev 158

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 root 5700d 21h /dbg_interface/trunk/bench/verilog/dbg_tb.v
145 Support for 2 CPUs added. igorm 7505d 04h /dbg_interface/trunk/bench/verilog/dbg_tb.v
142 Typo fixed. igorm 7505d 08h /dbg_interface/trunk/bench/verilog/dbg_tb.v
141 data_cnt_lim length changed to reduce number of warnings. igorm 7506d 03h /dbg_interface/trunk/bench/verilog/dbg_tb.v
140 CRC checking of incoming CRC added to all tasks. igorm 7506d 18h /dbg_interface/trunk/bench/verilog/dbg_tb.v
139 New release of the debug interface (3rd. release). igorm 7508d 21h /dbg_interface/trunk/bench/verilog/dbg_tb.v
138 Temp version before changing dbg interface. igorm 7515d 01h /dbg_interface/trunk/bench/verilog/dbg_tb.v
135 'hz changed to 1'hz because Icarus complains. igorm 7522d 01h /dbg_interface/trunk/bench/verilog/dbg_tb.v
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7567d 07h /dbg_interface/trunk/bench/verilog/dbg_tb.v
124 Display for VATS added. mohor 7572d 03h /dbg_interface/trunk/bench/verilog/dbg_tb.v
121 Port signals are all set to zero after reset. mohor 7575d 03h /dbg_interface/trunk/bench/verilog/dbg_tb.v
120 test stall_test added. mohor 7575d 06h /dbg_interface/trunk/bench/verilog/dbg_tb.v
117 Define name changed. mohor 7577d 03h /dbg_interface/trunk/bench/verilog/dbg_tb.v
116 Data latching changed when testing WB. mohor 7577d 03h /dbg_interface/trunk/bench/verilog/dbg_tb.v
115 More debug data added. mohor 7577d 07h /dbg_interface/trunk/bench/verilog/dbg_tb.v
114 CRC generation iand verification in bench changed. mohor 7577d 08h /dbg_interface/trunk/bench/verilog/dbg_tb.v
113 IDCODE test improved. mohor 7577d 09h /dbg_interface/trunk/bench/verilog/dbg_tb.v
111 Define tap_defines.v added to test bench. mohor 7578d 04h /dbg_interface/trunk/bench/verilog/dbg_tb.v
110 Waiting for "ready" improved. mohor 7578d 05h /dbg_interface/trunk/bench/verilog/dbg_tb.v
102 New version. mohor 7579d 23h /dbg_interface/trunk/bench/verilog/dbg_tb.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.