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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] [dbg_tb.v] - Rev 158

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Rev Log message Author Age Path
158 root 5693d 05h /dbg_interface/trunk/bench/verilog/dbg_tb.v
145 Support for 2 CPUs added. igorm 7497d 12h /dbg_interface/trunk/bench/verilog/dbg_tb.v
142 Typo fixed. igorm 7497d 16h /dbg_interface/trunk/bench/verilog/dbg_tb.v
141 data_cnt_lim length changed to reduce number of warnings. igorm 7498d 11h /dbg_interface/trunk/bench/verilog/dbg_tb.v
140 CRC checking of incoming CRC added to all tasks. igorm 7499d 02h /dbg_interface/trunk/bench/verilog/dbg_tb.v
139 New release of the debug interface (3rd. release). igorm 7501d 05h /dbg_interface/trunk/bench/verilog/dbg_tb.v
138 Temp version before changing dbg interface. igorm 7507d 09h /dbg_interface/trunk/bench/verilog/dbg_tb.v
135 'hz changed to 1'hz because Icarus complains. igorm 7514d 09h /dbg_interface/trunk/bench/verilog/dbg_tb.v
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7559d 15h /dbg_interface/trunk/bench/verilog/dbg_tb.v
124 Display for VATS added. mohor 7564d 11h /dbg_interface/trunk/bench/verilog/dbg_tb.v
121 Port signals are all set to zero after reset. mohor 7567d 11h /dbg_interface/trunk/bench/verilog/dbg_tb.v
120 test stall_test added. mohor 7567d 14h /dbg_interface/trunk/bench/verilog/dbg_tb.v
117 Define name changed. mohor 7569d 11h /dbg_interface/trunk/bench/verilog/dbg_tb.v
116 Data latching changed when testing WB. mohor 7569d 11h /dbg_interface/trunk/bench/verilog/dbg_tb.v
115 More debug data added. mohor 7569d 15h /dbg_interface/trunk/bench/verilog/dbg_tb.v
114 CRC generation iand verification in bench changed. mohor 7569d 16h /dbg_interface/trunk/bench/verilog/dbg_tb.v
113 IDCODE test improved. mohor 7569d 17h /dbg_interface/trunk/bench/verilog/dbg_tb.v
111 Define tap_defines.v added to test bench. mohor 7570d 12h /dbg_interface/trunk/bench/verilog/dbg_tb.v
110 Waiting for "ready" improved. mohor 7570d 13h /dbg_interface/trunk/bench/verilog/dbg_tb.v
102 New version. mohor 7572d 07h /dbg_interface/trunk/bench/verilog/dbg_tb.v

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