URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_cpu.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5778d 20h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
152	CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last check-in.	igorm	7576d 02h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
150	Zero is shifted out when CTRL_READ command is active.	igorm	7576d 21h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
143	Signals for easier debugging removed.	igorm	7583d 06h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
141	data_cnt_lim length changed to reduce number of warnings.	igorm	7584d 02h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
139	New release of the debug interface (3rd. release).	igorm	7586d 20h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
123	All flipflops are reset.	mohor	7650d 02h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
121	Port signals are all set to zero after reset.	mohor	7653d 02h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7656d 09h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7657d 21h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
102	New version.	mohor	7657d 22h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
101	Almost finished.	mohor	7657d 23h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v
100	* empty log message *	mohor	7659d 01h	/dbg_interface/trunk/rtl/verilog/dbg_cpu.v