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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_wb.v] - Rev 158

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Rev Log message Author Age Path
158 root 5778d 20h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
146 Changes for the FormalPRO. igorm 7582d 23h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
144 Port names and defines for the supported CPUs changed. igorm 7583d 04h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
141 data_cnt_lim length changed to reduce number of warnings. igorm 7584d 01h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
139 New release of the debug interface (3rd. release). igorm 7586d 20h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
138 Temp version before changing dbg interface. igorm 7592d 23h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
123 All flipflops are reset. mohor 7650d 02h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
121 Port signals are all set to zero after reset. mohor 7653d 02h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7656d 08h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
102 New version. mohor 7657d 22h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
99 cpu registers added. mohor 7659d 01h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
97 Working. mohor 7660d 04h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
95 Temp version. mohor 7660d 17h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
94 temp version. Resets will be changed in next version. mohor 7661d 04h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
93 tmp version. mohor 7662d 05h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
92 temp version. mohor 7665d 08h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
91 tmp version. mohor 7666d 03h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
90 tmp version. mohor 7666d 22h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
89 temp4 version. mohor 7668d 04h /dbg_interface/trunk/rtl/verilog/dbg_wb.v
88 temp3 version. mohor 7668d 23h /dbg_interface/trunk/rtl/verilog/dbg_wb.v

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