URL https://opencores.org/ocsvn/dblclockfft/dblclockfft/trunk

Subversion Repositories dblclockfft

[/] [dblclockfft/] [trunk/] [bench/] [cpp/] [plottst.m] - Rev 35

Rev	Log message	Author	Age	Path
28	This revision represents a lot of work to get the Verilator simulation to now match the FPGA performance. The big problem turned out to be in the bit reversal stage, where a '=' was used on a register instead of a '<='. Neither Verilator nor Vivado complained, but they each treated the result differently. In addition, a bug was traced to the soft butterfly, butterfly.v, whereby the delay through the butterfly did not properly change when the delay through the multiply changed. All of this has been fixed, and now appears to work and work well in both hardware and simulation.	dgisselq	3440d 18h	/dblclockfft/trunk/bench/cpp/plottst.m