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32 Fixed the makefile dependency on the static VERILATOR_ROOT. dgisselq 2946d 13h /dblclockfft/trunk/doc/src/spec.tex
27 Minor documentation change. dgisselq 3449d 18h /dblclockfft/trunk/doc/src/spec.tex
26 A lot of updates and upgrades in this release. Specifically, work took place
over the last several days to demonstrate this FFT on an FPGA. It was
demonstrated on the Xilinx Artix-7 found on a Basys-3 development board.
Part of the effort stemmed around making certain that the DSPs were used
optimally, part of it stemmed around making certain that various parts of the
FFT could use block RAM-type memories. The other massive change involved
removing as much unnecessary logic as possible, so that two 16-bit 1k FFTs
could fit onto this part--together with other glue logic. The bottom line,
though, is that it all now works. Specifically, I've tested it successfully
with

fftgen -f <FFTSIZE> -n 16 -m 16 -p 7 -c 1 -x 1

and with FFTSIZEs of 32, 64, 128, 256, 512, and 1024.

Oh, I should mention that there's also an undocumented DEBUG interface to the
part, and I fixed where the Verilog files went when given an argument, so
that they actually went to the directory specified. Minor updates have taken
place to the documentation format, making it match the documentation format
for other opencores projects that I've produced.

On a sadder note, the Verilator simulation fft_tb no longer works. (Yeah, get
that---the FFT implementation works but Verilator does not. Sigh).		 dgisselq 3449d 21h /dblclockfft/trunk/doc/src/spec.tex
22 Lot's of changes, mostly around getting this multiply to fit within a
particular FPGA. Specifically, we just added the capability of using
hardware multiplies to the command line options. Use them if you have
them, and it will simplify the operation of the FFT.		 dgisselq 3530d 14h /dblclockfft/trunk/doc/src/spec.tex
12 Minor changes to both class (trimmed the portlist and revision history
tables to match the text width), and the description of the io ports.
Specifically, i_left, the port that is broken out and described, had
mislabeled/misnumbered bits in the port list.

As this is a minor change, I will not update the revision--although perhaps
it should be.		 dgisselq 3540d 21h /dblclockfft/trunk/doc/src/spec.tex
11 Here's the full first draft of the specification, now complete. dgisselq 3540d 21h /dblclockfft/trunk/doc/src/spec.tex
10 I'm in the middle of building the spec. I've got most of the parts
complete, but the figure diagraming an FFT stage is still in the works.
I'm checking this in in the hopes that someone struggling to use this
will find this initial draft of the specification useful enough to
make their project work.		 dgisselq 3541d 09h /dblclockfft/trunk/doc/src/spec.tex

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