URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [cpu/] [cpu.v] - Rev 290

Rev	Log message	Author	Age	Path
290	Wishbone-compatible bus signals	hellwig	3403d 02h	/eco32/trunk/fpga/mc/src/cpu/cpu.v
288	new directory structure within fpga	hellwig	3403d 23h	/eco32/trunk/fpga/mc/src/cpu/cpu.v
204	changed TLB behavior on tbs instructions	hellwig	3740d 04h	/eco32/trunk/fpga/mc/src/cpu/cpu.v
181	hardware got BadAccess register; synthesizer result eco32.bit now included	hellwig	3758d 01h	/eco32/trunk/fpga/mc/src/cpu/cpu.v
120	hardware: in cpu/sregs change signal names di->din, do->dout	hellwig	3914d 08h	/eco32/trunk/fpga/mc/src/cpu/cpu.v
81	hardware: cpu now has a bad address register	hellwig	3929d 10h	/eco32/trunk/fpga/mc/src/cpu/cpu.v
75	hardware: cpu now equal to port-15	hellwig	3933d 00h	/eco32/trunk/fpga/mc/src/cpu/cpu.v
27	fpga implementation unpacked	hellwig	3939d 07h	/eco32/trunk/fpga/mc/src/cpu/cpu.v