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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [cpu/] [cpu.v] - Rev 313

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Rev Log message Author Age Path
290 Wishbone-compatible bus signals hellwig 3405d 10h /eco32/trunk/fpga/mc/src/cpu/cpu.v
288 new directory structure within fpga hellwig 3406d 07h /eco32/trunk/fpga/mc/src/cpu/cpu.v
204 changed TLB behavior on tbs instructions hellwig 3742d 12h /eco32/trunk/fpga/mc/src/cpu/cpu.v
181 hardware got BadAccess register; synthesizer result eco32.bit now included hellwig 3760d 09h /eco32/trunk/fpga/mc/src/cpu/cpu.v
120 hardware: in cpu/sregs change signal names di->din, do->dout hellwig 3916d 16h /eco32/trunk/fpga/mc/src/cpu/cpu.v
81 hardware: cpu now has a bad address register hellwig 3931d 18h /eco32/trunk/fpga/mc/src/cpu/cpu.v
75 hardware: cpu now equal to port-15 hellwig 3935d 07h /eco32/trunk/fpga/mc/src/cpu/cpu.v
27 fpga implementation unpacked hellwig 3941d 15h /eco32/trunk/fpga/mc/src/cpu/cpu.v

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