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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [tmr/] [tmr.v] - Rev 304

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Rev Log message Author Age Path
290 Wishbone-compatible bus signals hellwig 3379d 16h /eco32/trunk/fpga/mc/src/tmr/tmr.v
288 new directory structure within fpga hellwig 3380d 13h /eco32/trunk/fpga/mc/src/tmr/tmr.v
69 hardware: timer counts clock cycles, counter is readable hellwig 3910d 17h /eco32/trunk/fpga/mc/src/tmr/tmr.v
68 hardware: timer now equal to port-15 hellwig 3910d 20h /eco32/trunk/fpga/mc/src/tmr/tmr.v
67 fpga implementation update hellwig 3910d 23h /eco32/trunk/fpga/mc/src/tmr/tmr.v
27 fpga implementation unpacked hellwig 3915d 21h /eco32/trunk/fpga/mc/src/tmr/tmr.v

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