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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_cop.v] - Rev 361

Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4860d 23h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
352	Removed delayed assignments from rtl code	olof	4872d 00h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
351	Turn defines into parameters in eth_cop	olof	4880d 14h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4880d 15h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
346	Updated project location	olof	4882d 17h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
338		root	5686d 20h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
335	New directory structure.	root	5744d 01h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7839d 23h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
212	Minor $display change.	mohor	8085d 18h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
160	error acknowledge cycle termination added to display.	mohor	8116d 22h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	8142d 18h	/ethmac/branches/unneback/rtl/verilog/eth_cop.v