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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_fifo.v] - Rev 361

Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4857d 10h	/ethmac/branches/unneback/rtl/verilog/eth_fifo.v
352	Removed delayed assignments from rtl code	olof	4868d 12h	/ethmac/branches/unneback/rtl/verilog/eth_fifo.v
346	Updated project location	olof	4879d 05h	/ethmac/branches/unneback/rtl/verilog/eth_fifo.v
338		root	5683d 07h	/ethmac/branches/unneback/rtl/verilog/eth_fifo.v
335	New directory structure.	root	5740d 12h	/ethmac/branches/unneback/rtl/verilog/eth_fifo.v
330	Warning fixes.	igorm	7217d 09h	/ethmac/branches/unneback/rtl/verilog/eth_fifo.v
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8253d 09h	/ethmac/branches/unneback/rtl/verilog/eth_fifo.v
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8281d 09h	/ethmac/branches/unneback/rtl/verilog/eth_fifo.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8329d 06h	/ethmac/branches/unneback/rtl/verilog/eth_fifo.v