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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 362

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Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4861d 01h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
352	Removed delayed assignments from rtl code	olof	4872d 02h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
346	Updated project location	olof	4882d 19h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
338		root	5686d 21h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
335	New directory structure.	root	5744d 02h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
333	Some small fixes + some troubles fixed.	igorm	7192d 16h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
325	Defer indication fixed.	igorm	7221d 02h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
276	Defer indication changed.	tadejm	7973d 23h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	8043d 10h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	8051d 14h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	8113d 22h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
146	CarrierSenseLost status is not set when working in loopback mode.	mohor	8121d 18h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
126	InvalidSymbol generation changed.	mohor	8162d 18h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8256d 23h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
70	Small fixes.	mohor	8320d 02h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8322d 19h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
43	Tx status is written back to the BD.	mohor	8327d 03h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
42	Rx status is written back to the BD.	mohor	8329d 20h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
37	Link in the header changed.	mohor	8346d 02h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8442d 04h	/ethmac/branches/unneback/rtl/verilog/eth_macstatus.v

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 362

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