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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_random.v] - Rev 361

Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4857d 10h	/ethmac/branches/unneback/rtl/verilog/eth_random.v
352	Removed delayed assignments from rtl code	olof	4868d 12h	/ethmac/branches/unneback/rtl/verilog/eth_random.v
346	Updated project location	olof	4879d 05h	/ethmac/branches/unneback/rtl/verilog/eth_random.v
338		root	5683d 07h	/ethmac/branches/unneback/rtl/verilog/eth_random.v
335	New directory structure.	root	5740d 12h	/ethmac/branches/unneback/rtl/verilog/eth_random.v
285	Binary operator used instead of unary (xnor).	mohor	7836d 11h	/ethmac/branches/unneback/rtl/verilog/eth_random.v
37	Link in the header changed.	mohor	8342d 12h	/ethmac/branches/unneback/rtl/verilog/eth_random.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8438d 13h	/ethmac/branches/unneback/rtl/verilog/eth_random.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8512d 08h	/ethmac/branches/unneback/rtl/verilog/eth_random.v