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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_registers.v] - Rev 363

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Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4863d 00h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
352	Removed delayed assignments from rtl code	olof	4874d 01h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
346	Updated project location	olof	4884d 18h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
338		root	5688d 21h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
335	New directory structure.	root	5746d 02h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
333	Some small fixes + some troubles fixed.	igorm	7194d 16h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7523d 20h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
320	TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.	igorm	7524d 00h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7689d 17h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
283	RxBDAddress was updated also when value to r_TxBDNum was written with greater value than allowed.	mohor	7897d 19h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	8045d 10h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	8047d 18h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	8052d 17h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
164	Ethernet debug registers removed.	mohor	8118d 01h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
147	ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to the control frames connected.	mohor	8123d 17h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
143	Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.	mohor	8139d 20h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
141	Syntax error fixed.	mohor	8142d 13h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
140	Syntax error fixed.	mohor	8142d 13h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
139	Synchronous reset added to all registers. Defines used for width. r_MiiMRst changed from bit position 10 to 9.	mohor	8142d 14h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	8144d 17h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_registers.v] - Rev 363

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