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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 363

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Rev Log message Author Age Path
361 created branch unneback unneback 4863d 00h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
352 Removed delayed assignments from rtl code olof 4874d 01h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
346 Updated project location olof 4884d 18h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
338 root 5688d 20h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
335 New directory structure. root 5746d 02h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
330 Warning fixes. igorm 7222d 23h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7666d 23h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
306 Lapsus fixed (!we -> ~we). simons 7667d 21h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7689d 17h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
302 mbist signals updated according to newest convention markom 7716d 04h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
297 Artisan ram instance added. simons 7779d 19h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
227 Changed BIST scan signals. tadejm 8079d 19h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
210 BIST added. mohor 8087d 19h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 8104d 17h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8166d 19h /ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v

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