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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_top.v] - Rev 363

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Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4860d 13h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
352	Removed delayed assignments from rtl code	olof	4871d 14h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
349	Make all parameters configurable from top level	olof	4881d 05h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
346	Updated project location	olof	4882d 07h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
338		root	5686d 09h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
335	New directory structure.	root	5743d 14h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
333	Some small fixes + some troubles fixed.	igorm	7192d 04h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
327	Defer indication fixed.	igorm	7220d 13h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7521d 09h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7687d 06h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
302	mbist signals updated according to newest convention	markom	7713d 17h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7724d 09h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
276	Defer indication changed.	tadejm	7973d 11h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
272	When control packets were received, they were ignored in some cases.	tadejm	7981d 11h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7982d 12h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	8042d 22h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
255	TPauseRq synchronized to tx_clk.	mohor	8044d 00h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	8045d 06h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	8045d 07h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
248	wb_rst_i is used for MIIM reset.	mohor	8046d 07h	/ethmac/branches/unneback/rtl/verilog/eth_top.v

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_top.v] - Rev 363

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