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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 361

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Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4857d 10h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
352	Removed delayed assignments from rtl code	olof	4868d 12h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
349	Make all parameters configurable from top level	olof	4878d 03h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
346	Updated project location	olof	4879d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
338		root	5683d 07h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
335	New directory structure.	root	5740d 12h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
333	Some small fixes + some troubles fixed.	igorm	7189d 02h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
329	Defer indication fixed.	igorm	7217d 10h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
323	Accidently deleted line put back.	igorm	7514d 12h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7518d 07h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7684d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
302	mbist signals updated according to newest convention	markom	7710d 14h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
280	Reset has priority in some flipflops.	mohor	7970d 07h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
278	A new bug (entered with previous update) fixed. When abort occured sometimes data transmission was blocked.	mohor	7970d 08h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
272	When control packets were received, they were ignored in some cases.	tadejm	7978d 08h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7979d 10h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7980d 10h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	8039d 09h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	8039d 20h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	8042d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 361

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