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[/] [ethmac/] [tags/] [rel_23/] [rtl/] [verilog/] [eth_defines.v] - Rev 340

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338 root 5500d 03h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
335 New directory structure. root 5557d 08h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7500d 23h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7500d 23h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
302 mbist signals updated according to newest convention markom 7527d 10h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
297 Artisan ram instance added. simons 7591d 01h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7653d 06h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7859d 00h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7863d 03h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
238 Defines fixed to use generic RAM by default. mohor 7877d 00h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
232 fpga define added. mohor 7884d 23h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7899d 01h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
211 Bist added. mohor 7899d 01h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7915d 23h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7934d 23h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.		 mohor 7953d 20h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7955d 22h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7978d 02h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8059d 08h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8068d 09h /ethmac/tags/rel_23/rtl/verilog/eth_defines.v

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