OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_25/] [bench/] [verilog/] [tb_ethernet.v] - Rev 338

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 5592d 16h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
335 New directory structure. root 5649d 22h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
316 This commit was manufactured by cvs2svn to create tag 'rel_25'. 7570d 19h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 7570d 19h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 7620d 00h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 7677d 19h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7878d 16h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7879d 18h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 7887d 12h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 7943d 15h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 7948d 14h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7949d 05h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7949d 18h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7951d 11h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7951d 14h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7956d 18h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7983d 15h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7983d 18h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7992d 18h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 8011d 17h /ethmac/tags/rel_25/bench/verilog/tb_ethernet.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.