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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 344

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Rev Log message Author Age Path
344 bit 9 in phy control register is self clearing olof 4911d 15h /ethmac/trunk/bench/verilog/tb_ethernet.v
343 Address miss should not be asserted on short frames olof 4915d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
342 Added cast to avoid inequality when comparing different data types olof 4915d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
338 root 5709d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
335 New directory structure. root 5766d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
334 Minor fixes for Icarus simulator. igorm 7214d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
331 Tests for delayed CRC and defer indication added. igorm 7243d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 7575d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 7687d 17h /ethmac/trunk/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 7736d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 7794d 17h /ethmac/trunk/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7995d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7996d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 8004d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 8060d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 8065d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 8066d 03h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 8066d 15h /ethmac/trunk/bench/verilog/tb_ethernet.v
254 Temp version. mohor 8068d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 8068d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v

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