OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 346

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
346 Updated project location olof 4882d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
345 Temporarily disable failing tests olof 4882d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
344 bit 9 in phy control register is self clearing olof 4888d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
343 Address miss should not be asserted on short frames olof 4892d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
342 Added cast to avoid inequality when comparing different data types olof 4892d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
338 root 5686d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
335 New directory structure. root 5743d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
334 Minor fixes for Icarus simulator. igorm 7191d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v
331 Tests for delayed CRC and defer indication added. igorm 7220d 15h /ethmac/trunk/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 7552d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 7664d 15h /ethmac/trunk/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 7713d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 7771d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7972d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7973d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 7981d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 8037d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 8042d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 8043d 02h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 8043d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.