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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet_with_cop.v] - Rev 366

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364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4840d 02h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4845d 04h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
346 Updated project location olof 4862d 05h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
338 root 5666d 07h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
335 New directory structure. root 5723d 13h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
302 mbist signals updated according to newest convention markom 7693d 15h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
299 Artisan RAMs added. mohor 7751d 10h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
227 Changed BIST scan signals. tadejm 8057d 06h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
216 Bist signals added. mohor 8064d 09h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 8087d 06h /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v

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