URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_clockgen.v] - Rev 348

Rev	Log message	Author	Age	Path
346	Updated project location	olof	4858d 00h	/ethmac/trunk/rtl/verilog/eth_clockgen.v
338		root	5662d 02h	/ethmac/trunk/rtl/verilog/eth_clockgen.v
335	New directory structure.	root	5719d 07h	/ethmac/trunk/rtl/verilog/eth_clockgen.v
330	Warning fixes.	igorm	7196d 05h	/ethmac/trunk/rtl/verilog/eth_clockgen.v
37	Link in the header changed.	mohor	8321d 07h	/ethmac/trunk/rtl/verilog/eth_clockgen.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8417d 09h	/ethmac/trunk/rtl/verilog/eth_clockgen.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8491d 03h	/ethmac/trunk/rtl/verilog/eth_clockgen.v