URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Rev 348

Rev	Log message	Author	Age	Path
346	Updated project location	olof	4858d 00h	/ethmac/trunk/rtl/verilog/eth_cop.v
338		root	5662d 02h	/ethmac/trunk/rtl/verilog/eth_cop.v
335	New directory structure.	root	5719d 07h	/ethmac/trunk/rtl/verilog/eth_cop.v
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7815d 06h	/ethmac/trunk/rtl/verilog/eth_cop.v
212	Minor $display change.	mohor	8061d 01h	/ethmac/trunk/rtl/verilog/eth_cop.v
160	error acknowledge cycle termination added to display.	mohor	8092d 05h	/ethmac/trunk/rtl/verilog/eth_cop.v
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	8118d 00h	/ethmac/trunk/rtl/verilog/eth_cop.v