URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Rev 353

Rev	Log message	Author	Age	Path
352	Removed delayed assignments from rtl code	olof	4847d 16h	/ethmac/trunk/rtl/verilog/eth_cop.v
351	Turn defines into parameters in eth_cop	olof	4856d 06h	/ethmac/trunk/rtl/verilog/eth_cop.v
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4856d 06h	/ethmac/trunk/rtl/verilog/eth_cop.v
346	Updated project location	olof	4858d 09h	/ethmac/trunk/rtl/verilog/eth_cop.v
338		root	5662d 11h	/ethmac/trunk/rtl/verilog/eth_cop.v
335	New directory structure.	root	5719d 16h	/ethmac/trunk/rtl/verilog/eth_cop.v
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7815d 14h	/ethmac/trunk/rtl/verilog/eth_cop.v
212	Minor $display change.	mohor	8061d 10h	/ethmac/trunk/rtl/verilog/eth_cop.v
160	error acknowledge cycle termination added to display.	mohor	8092d 13h	/ethmac/trunk/rtl/verilog/eth_cop.v
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	8118d 09h	/ethmac/trunk/rtl/verilog/eth_cop.v