URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Rev 353

Rev	Log message	Author	Age	Path
352	Removed delayed assignments from rtl code	olof	4899d 05h	/ethmac/trunk/rtl/verilog/eth_fifo.v
346	Updated project location	olof	4909d 22h	/ethmac/trunk/rtl/verilog/eth_fifo.v
338		root	5714d 00h	/ethmac/trunk/rtl/verilog/eth_fifo.v
335	New directory structure.	root	5771d 06h	/ethmac/trunk/rtl/verilog/eth_fifo.v
330	Warning fixes.	igorm	7248d 03h	/ethmac/trunk/rtl/verilog/eth_fifo.v
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8284d 02h	/ethmac/trunk/rtl/verilog/eth_fifo.v
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8312d 02h	/ethmac/trunk/rtl/verilog/eth_fifo.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8359d 23h	/ethmac/trunk/rtl/verilog/eth_fifo.v