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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_maccontrol.v] - Rev 347

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Rev	Log message	Author	Age	Path
346	Updated project location	olof	4872d 22h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v
338		root	5677d 00h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v
335	New directory structure.	root	5734d 06h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v
272	When control packets were received, they were ignored in some cases.	tadejm	7972d 02h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	8033d 14h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v
256	TxDone and TxAbort changed so they're not propagated to the wishbone module when control frame is transmitted.	mohor	8034d 15h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	8035d 22h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v
37	Link in the header changed.	mohor	8336d 05h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8432d 07h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8506d 01h	/ethmac/trunk/rtl/verilog/eth_maccontrol.v

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