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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 365

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Rev	Log message	Author	Age	Path
352	Removed delayed assignments from rtl code	olof	4706d 11h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
346	Updated project location	olof	4717d 04h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
338		root	5521d 06h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
335	New directory structure.	root	5578d 11h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
333	Some small fixes + some troubles fixed.	igorm	7027d 01h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
325	Defer indication fixed.	igorm	7055d 11h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
276	Defer indication changed.	tadejm	7808d 08h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7877d 19h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7885d 23h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7948d 06h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
146	CarrierSenseLost status is not set when working in loopback mode.	mohor	7956d 03h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
126	InvalidSymbol generation changed.	mohor	7997d 03h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8091d 07h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
70	Small fixes.	mohor	8154d 11h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8157d 04h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
43	Tx status is written back to the BD.	mohor	8161d 12h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
42	Rx status is written back to the BD.	mohor	8164d 05h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
37	Link in the header changed.	mohor	8180d 11h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8276d 12h	/ethmac/trunk/rtl/verilog/eth_macstatus.v
18	Few little NCSIM warnings fixed.	mohor	8314d 07h	/ethmac/trunk/rtl/verilog/eth_macstatus.v

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 365

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