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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_outputcontrol.v] - Rev 351

Rev	Log message	Author	Age	Path
346	Updated project location	olof	4904d 20h	/ethmac/trunk/rtl/verilog/eth_outputcontrol.v
338		root	5708d 23h	/ethmac/trunk/rtl/verilog/eth_outputcontrol.v
335	New directory structure.	root	5766d 04h	/ethmac/trunk/rtl/verilog/eth_outputcontrol.v
109	Comment removed.	mohor	8200d 18h	/ethmac/trunk/rtl/verilog/eth_outputcontrol.v
37	Link in the header changed.	mohor	8368d 03h	/ethmac/trunk/rtl/verilog/eth_outputcontrol.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8464d 05h	/ethmac/trunk/rtl/verilog/eth_outputcontrol.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8537d 23h	/ethmac/trunk/rtl/verilog/eth_outputcontrol.v